给二进制转BCD模块

default:
begin state <= 0; start_sig_r <= 1’b0; end
endcase
end

SEG_NUMD=8’h5e,

SEG_NUM6=8’h7d,

 

 

module smg_encoder_module(clk,rst_n,num,smg_data);

 

 

5:
begin start_sig_r <= 1’b0; state <= state + 1; end

SEG_NUM9=8’h6f,

SEG_NUMC=8’h39,

assign smg_data=smg_data_r;

//整出下落沿脉冲
reg sck_flag1;
reg sck_flag2;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
sck_flag1 <= 1’b1;
sck_flag2 <= 1’b1;
end
else
begin
sck_flag1 <= sck_r;
sck_flag2 <= sck_flag1;
end
end

http://stepfpga.ecbcamp.com/doc/%E7%9B%B4%E6%B5%81%E7%94%B5%E5%8E%8B%E6%B5%8B%E9%87%8F
相关资料

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
beep_count <= 0;
end
else if(alarm)
beep_count <= 27’d125000000;
else if(beep_count>0)
beep_count <= beep_count – 1;

SEG_NUMB=8’h7c,

SEG_NUMF=8’h71;

SEG_NUM2=8’h5b,

assign start_sig = start_sig_r;
assign duan_wei_data = duan_wei_data_r;
endmodule

 

5:begin
seg_flash_data_r<=4’b0010;
bcd_seg_display_num_r[15:0] <=
{bcd_min_ten_cnt,bcd_min_one_cnt,bcd_sec_ten_cnt,bcd_sec_one_cnt};
if(key_value==12&key_flag==1)begin
if(bcd_sec_ten_cnt==5)bcd_sec_ten_cnt<=0;else
bcd_sec_ten_cnt<=bcd_sec_ten_cnt+1;end end

 

wire alarm
=(bcd_hour_ten_cnt==1&&bcd_hour_one_cnt==2&&bcd_min_ten_cnt==0&&bcd_min_one_cnt==0&&bcd_sec_ten_cnt==0&&bcd_sec_one_cnt==0);

 

 

SEG_NUM8=8’h7f,

6:
if(done_sig) begin duan_wei_data_r[15:0] <=
{(seg_flash_data[1]?8’h00:num1_ten_smg_data),Flag_1S?8’h1b:8’h
b}; state <= state + 1; start_sig_r <= 1’b1;
end//{num1_ten_smg_data,4’h2,(4’hb&seg_flash_data)}; state <=
state + 1; start_sig_r <= 1’b1; end

将出口的8位255的BCD码对应成3.3V的体现,用输出的Q[7:0]去乘上13,给二进制转BCD模块,最终数码管展现控制小数点的职位一定于再除以1000。

SEG_NUM4=8’h66,

//由0到f的编码为

//分出5M频率

module ad_collect
(
input sddata,
input rst_n,
output reg cs,
output reg sclk,
input clk,
output [7:0]seg_data,
output done
);

input clk;
input rst_n;
input [3:0]num;
output [7:0]smg_data;

reg [7:0]cnt;
reg[4:0]state;
reg[7:0]data;
reg rdone;

/*共阴极数码管: 位选为低电平(即0)选中数码管;
各段选为高电平(即1接+5V时)选中各数码段;*/

//那是一个选用Verilog
HDL编写的带使能端的8-bit二进制转BCD码程序,具有占用资源少、移植性好、扩充方便的风味。
/********************************************\
Filrst_nme : B_BCD.v Author : Medied.Lee
Description : a 8-bit binary-to-bcd module
Revision : 2010/11/20 Company :
\********************************************/
module bin_bcd(rst_n,binary,bcd);
//rst_n为使能端,binary为待转换的二进制数,bcd为转移后的BCD码
parameter B_SIZE=12;
//B_SIZE为二进制数所占的位数,可依照需求开展增添
input binary,rst_n;//rst_n高电平有效,低电平常
output bcd;
wire rst_n;
wire [B_SIZE-1:0] binary;
reg [B_SIZE-1:0] bin;
reg [B_SIZE+3:0] bcd; // bcd的长度应根据实际景况开展改动
reg [B_SIZE+3:0] result; //result的长度=bcd的长度
always@(binary or rst_n)
begin
bin= binary;
result = 0;
if(rst_n == 0)
bcd <= 0;
else
begin
repeat(B_SIZE-1)//使用repeat语句举办巡回计算
begin
result[0] = bin[B_SIZE-1];
if ( result[3:0] > 4 )
result[3:0]=result[3:0]+ 4’d3;
if(result[7:4]> 4)
result[7:4]=result[7:4]+4’d3;
if(result[11:8]>4)
result[11:8] = result[11:8]+4’d3;
//扩充时应参考此三条if语句续写
if(result[15:12]>4)
result[15:12]= result[15:12]+ 4’d3;
result=result<<1;
bin=bin<<1; end
result[0]= bin[B_SIZE-1];
bcd<=result;
end
end
endmodule

module smg_encoder_module(clk,rst_n,num,smg_data);

//Finite State Machine,
reg shift_flag = 0;
reg[15:0] data_reg;
reg[2:0] data_state=IDLE;
reg[2:0] data_state_back;
reg[3:0] data_state_cnt=0;
reg[5:0] shift_cnt=0;
reg[25:0] delay_cnt=0;
always@(posedge clk_in or negedge rst_n_in) begin
if(!rst_n_in) begin
data_state<=IDLE;
data_state_cnt<=0;
end else begin
case (data_state)
IDLE: begin
data_state_cnt<=data_state_cnt+1;
case(data_state_cnt)
0: begin
data_reg<={{1’b1,datah_f[6:0]}, 8’h0e};
data_state<=WRITE;data_state_back<=IDLE;
end
1: begin
data_reg<={datal_f,8’h0d};
data_state<=WRITE;data_state_back<=IDLE;
end
2: begin
data_reg<={datah_m,8’h0b};
data_state<=WRITE;data_state_back<=IDLE;
end
3: begin
data_reg<={datal_m,8’h07};
data_state<=WRITE;data_state_back<=IDLE;
end
4: begin data_state_cnt<=0; end
default;
endcase
end
WRITE: begin
if(!shift_flag) begin
if (clk_div_state==CLK_FALLING_DEGE) begin
if (shift_cnt==10) rclk_out<=LOW;
if (shift_cnt==16) begin
shift_cnt<=0;
rclk_out<=HIGH;
data_state<=data_state_back;
end else begin
sclk_out<=LOW;
sdio_out<=data_reg[15];
shift_flag <= 1;
end
end
end else begin
if (clk_div_state==CLK_RISING_DEGE) begin
data_reg<={data_reg[14:0], data_reg[15]};
shift_cnt<=shift_cnt+1;
sclk_out<=HIGH;
shift_flag <= 0;
end
end
end
DELAY: begin
if(delay_cnt==DELAY_PERIOD) begin
data_state<=IDLE;
delay_cnt<=0;
end else delay_cnt<=delay_cnt+1;
end

SEG_NUM2=8’h5b,

//Divide clk_div 4 state,
//RISING and FALLING state is keeped one cycle of clk_in, like a
pulse.
reg[1:0] clk_div_state=CLK_L;
always@(posedge clk_in or negedge rst_n_in) begin
if(!rst_n_in) clk_div_state<=CLK_L;
else case(clk_div_state)
CLK_L: begin
if (clk_div) clk_div_state<=CLK_RISING_DEGE;
else clk_div_state<=CLK_L;
end
CLK_RISING_DEGE :clk_div_state<=CLK_H;
CLK_H:begin
if (!clk_div) clk_div_state<=CLK_FALLING_DEGE;
else clk_div_state<=CLK_H;
end
CLK_FALLING_DEGE:clk_div_state<=CLK_L;
default;
endcase
end

4: begin
seg_flash_data_r<=4’b0001;
bcd_seg_display_num_r[15:0] <=
{bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if(key_value==9&key_flag==1)begin
if(bcd_min_one_cnt==9)bcd_min_one_cnt<=0;else
bcd_min_one_cnt<=bcd_min_one_cnt+1;end end

出口的结果通过数码管译码

呈现模块

澳门皇冠官网app 1

1:
begin start_sig_r <= 1’b0; state<=4; end

default: smg_data_r <= 8’b00000000;
endcase
end

 

module seg_chg
(
input clk_in, //25mhz
input rst_n_in, //active with low
input [7:0] datah_f,
input [7:0] datal_f,
input [7:0] datah_m,
input [7:0] datal_m,
output reg rclk_out, //74HC595 RCK
output reg sclk_out, //74HC595 SCK
output reg sdio_out //74HC595 SER
);

end
assign Flag_1S = Flag_1S_r;
wire key_in;
debounce xiaodou

SEG_NUM1=8’h06,

SEG_NUM7=8’h07,

endmodule

设计的RTL结构

reg[24:0] cnt;
reg clk_div_1Hz;
always@(posedge clk_in or negedge rst_n_in)
begin
if(!rst_n_in) begin
cnt<=0;
clk_div_1Hz<=0;
end else if(cnt==(CLK_DIV_PULSE_PERIOD-1)) begin
cnt<=0;
clk_div_1Hz<=1;
end else begin
cnt<=cnt+1;
clk_div_1Hz<=0;
end
end

SEG_NUM3=8’h4f,

/*共阴极数码管: 位选为低电平(即0)选中数码管;
各段选为高电平(即1接+5V时)选中各数码段;*/

拍卖模块落成形式切换与计数,4位数码管解码后
595control模块控制数码管的点闪动以及调时位的半秒闪动,595function模块16位串行输出给595使得数码管突显

 

reg [15:0]duan_wei_data_r;
reg start_sig_r;
reg [3:0]state;

澳门皇冠官网app 2

1 :begin seg_flash_data_r<=4’b1000;
bcd_seg_display_num_r[15:0] <=
{bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if(key_value==4&key_flag==1)begin
if(bcd_hour_ten_cnt==2)bcd_hour_ten_cnt<=0;else
bcd_hour_ten_cnt<=bcd_hour_ten_cnt+1;end end

RTL结构图

assign alarm_beep = (beep_count>0 && ((beep_count[24]&&
beep_count[14])||(~beep_count[24]&& beep_count[13])));
endmodule

default;
endcase
end
end

4:
if(done_sig) begin duan_wei_data_r[15:0] <=
{(seg_flash_data[2]?8’h00:num2_one_smg_data),Flag_1S?8’h1d:8’h2d};state
<= state + 1; start_sig_r <= 1’b1;
end//{num2_one_smg_data,4’h2,(4’hd&seg_flash_data)};state <=
state + 1; start_sig_r <= 1’b1; end

endmodule

assign done_sig = done_sig_r;
assign dout = dout_r;
assign rck = rck_r;
assign sck = sck_r;

 

 

管脚分配

 

SEG_NUMF=8’h71;

3:begin seg_flash_data_r<=4’b0001;
if(key_value==6&key_flag==1)seg_flash_data_r[3:0] <=
{seg_flash_data_r[2:0],seg_flash_data_r[3]};
if(key_value==14&key_flag==1)seg_flash_data_r[3:0] <=
{seg_flash_data_r[0],seg_flash_data_r[3:1]};
bcd_seg_display_num_r[15:0] <=
{bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if(seg_flash_data_r[0]==1&key_value==13&key_flag==1)begin
if(bcd_min_one_cnt==9)bcd_sec_one_cnt<=0; else
bcd_sec_one_cnt<=bcd_sec_one_cnt+1;end
if(seg_flash_data_r[1]==1&key_value==12&key_flag==1)begin
if(bcd_min_ten_cnt==5)bcd_sec_ten_cnt<=0;else
bcd_sec_ten_cnt<=bcd_sec_ten_cnt+1;end
if(seg_flash_data_r[2]==1&key_value==5&key_flag==1)begin
if(bcd_hour_one_cnt==9)bcd_hour_one_cnt<=0;else
bcd_hour_one_cnt<=bcd_hour_one_cnt+1;end
if(seg_flash_data_r[3]==1&key_value==4&key_flag==1)begin
if(bcd_hour_ten_cnt==2)bcd_hour_ten_cnt<=0;else
bcd_hour_ten_cnt<=bcd_hour_ten_cnt+1;end end*/

 

assign smg_data=smg_data_r;

//clk_div = clk_in/CLK_DIV_PERIOD
reg clk_div;
reg[11:0] clk_cnt=0;
always@(posedge clk_in or negedge rst_n_in) begin
if(!rst_n_in) clk_cnt<=0;
else begin
clk_cnt<=clk_cnt+1;
if(clk_cnt==(CLK_DIV_PERIOD-1)) clk_cnt<=0;
if(clk_cnt<(CLK_DIV_PERIOD/2)) clk_div<=0;
else clk_div<=1;
end
end

always @(posedge clk or negedge rst_n)
if(!rst_n) begin
bcd_sec_one_cnt<=0;bcd_sec_ten_cnt<=0;bcd_min_one_cnt<=0;bcd_min_ten_cnt<=0;bcd_hour_one_cnt<=0;bcd_hour_ten_cnt<=0;seg_flash_data_r<=4’b0000;end
else
begin
case(mode)
0: begin seg_flash_data_r<=4’b0000;
bcd_seg_display_num_r[15:0] <=
{bcd_min_ten_cnt,bcd_min_one_cnt,bcd_sec_ten_cnt,bcd_sec_one_cnt};
if(count1 == T_1S)begin if(bcd_sec_one_cnt==9)
begin bcd_sec_one_cnt<=0; if(bcd_sec_ten_cnt==5)
begin bcd_sec_ten_cnt<=0;if(bcd_min_one_cnt==9)
begin bcd_min_one_cnt<=0;if(bcd_min_ten_cnt==5)
begin
bcd_min_ten_cnt<=0;if(bcd_hour_ten_cnt==2&&bcd_hour_one_cnt==3)begin
bcd_hour_ten_cnt<=0;bcd_hour_one_cnt<=0;end
else if(bcd_hour_one_cnt==9)begin
bcd_hour_one_cnt<=0;bcd_hour_ten_cnt<=bcd_hour_ten_cnt+1;end

 

SEG_NUM5=8’h6d,

always@(posedge clk or negedge rst_n ) begin
if(cs==0)begin sclk<=!sclk; cnt<=cnt+1;end
if(!rst_n)begin cs<=1;state<=0;cnt<=0;sclk<=1;rdone=0;end
else
begin
case(state)
0:if(rst_n==1)begin cs<=0;state<=state+1;end
1:if(cnt==8) begin data[7]<=sddata;state<=state+1;rdone=0;end
2:if(cnt==10) begin data[6]<=sddata;state<=state+1;rdone=0;end
3:if(cnt==12) begin data[5]<=sddata;state<=state+1;rdone=0;end
4:if(cnt==14) begin data[4]<=sddata;state<=state+1;rdone=0;end
5:if(cnt==16) begin data[3]<=sddata;state<=state+1;rdone=0;end
6:if(cnt==18) begin data[2]<=sddata;state<=state+1;rdone=0;end
7:if(cnt==20) begin data[1]<=sddata;state<=state+1;rdone=0;end
8:if(cnt==22) begin
data[0]<=sddata;;state<=state+1;rdone=0;end
9:if(cnt==32) begin cs<=1;state<=state+1;sclk<=0;rdone=1;end
10: begin cnt<=cnt+1;if(cnt==42)begin
cnt<=0;state<=0;rdone=0;end end
endcase
end
end
assign done=rdone;
assign seg_data=rdone?data[7:0]:seg_data;

default: begin dout_r <= 0; state <= 0; done_sig_r <= 1’b0;
end
endcase
end

reg [7:0]smg_data_r;

澳门皇冠官网app 3

终极通过串行数据发送数据给595输出

reg [3:0]bcd_sec_one_cnt;
reg [3:0]bcd_min_one_cnt;
reg [3:0]bcd_hour_one_cnt;
reg [3:0]bcd_sec_ten_cnt;
reg [3:0]bcd_min_ten_cnt;
reg [3:0]bcd_hour_ten_cnt;
reg[3:0] seg_flash_data_r;
wire [15:0] bcd_seg_display_num;
reg[2:0] mode;
reg [15:0] bcd_seg_display_num_r;

parameter CLK_DIV_PERIOD=3900; //related with clk_div’s frequency
parameter DELAY_PERIOD=10000; //related with delay time and refresh
frequency
parameter CLK_DIV_PULSE_PERIOD=25000000; //related with
clk_div_pulse_out’s frequency
parameter CLK_L=2’d0;
parameter CLK_H=2’d1;
parameter CLK_RISING_DEGE=2’d2;
parameter CLK_FALLING_DEGE=2’d3;
parameter IDLE=3’d0;
parameter WRITE=3’d1;
parameter DELAY=3’d2;
parameter LOW =1’b0;
parameter HIGH =1’b1;
//initial for memory register

module
seg595_control_module(clk,rst_n,num1_ten_smg_data,num1_one_smg_data,num2_ten_smg_data,num2_one_smg_data,seg_flash_data,duan_wei_data,Flag_1S,start_sig,done_sig);
input clk;
input rst_n;
input [7:0] num1_ten_smg_data;
input [7:0] num1_one_smg_data;
input [7:0] num2_ten_smg_data;
input [7:0] num2_one_smg_data;
input [3:0] seg_flash_data;
output [15:0]duan_wei_data;
output start_sig;
input done_sig;
input Flag_1S;

SEG_NUMC=8’h39,

6:begin
seg_flash_data_r<=4’b0001;
bcd_seg_display_num_r[15:0] <=
{bcd_min_ten_cnt,bcd_min_one_cnt,bcd_sec_ten_cnt,bcd_sec_one_cnt};
if(key_value==13&key_flag==1)begin
if(bcd_sec_one_cnt==9)bcd_sec_one_cnt<=0; else
bcd_sec_one_cnt<=bcd_sec_one_cnt+1;end end
//default:begin
bcd_sec_one_cnt<=0;bcd_sec_ten_cnt<=0;bcd_min_one_cnt<=0;bcd_min_ten_cnt<=0;bcd_hour_one_cnt<=0;bcd_hour_ten_cnt<=0;end
endcase
end
assign seg_flash_data[3:0] = Flag_1S_r
?seg_flash_data_r[3:0]:4’b0000;
assign bcd_seg_display_num[15:0] =
bcd_seg_display_num_r[15:0];

SEG_NUM3=8’h4f,

reg [26:0]beep_count;

采访模块运用SPI 通讯 MISO方式收集数据

 

SEG_NUM7=8’h07,

8:
if(done_sig) begin duan_wei_data_r[15:0] <=
{(seg_flash_data[0]?8’h00:num1_one_smg_data),Flag_1S?8’h17:8’h27};
state <= state + 1; start_sig_r <= 1’b1;
end//{num1_one_smg_data,4’h2,(4’h7&seg_flash_data)}; state <=
state + 1; start_sig_r <= 1’b1; end

parameter
SEG_NUM0=8’h3f,

 

SEG_NUMA=8’h77,

7:
begin start_sig_r <= 1’b0; state <= state + 1; end

input clk;
input rst_n;
input [3:0]num;
output [7:0]smg_data;

SEG_NUMB=8’h7c,

SEG_NUME=8’h79,

module
seg595_function_module(clk,rst_n,duan_wei_data,start_sig,done_sig,sck,rck,dout);
input clk;
input rst_n;
input [15:0]duan_wei_data;
input start_sig;
output done_sig;
output sck;
output rck;
output dout;

 

endmodule

SEG_NUM6=8’h7d,

 

SEG_NUM4=8’h66,

SEG_NUMA=8’h77,

SEG_NUM5=8’h6d,

else bcd_hour_one_cnt<=bcd_hour_one_cnt+1;
end
else bcd_min_ten_cnt<=bcd_min_ten_cnt+1;end
else bcd_min_one_cnt<=bcd_min_one_cnt+1;end
else bcd_sec_ten_cnt<=bcd_sec_ten_cnt+1;end
else bcd_sec_one_cnt<=bcd_sec_one_cnt+1;end end
/* 1: begin seg_flash_data_r <= 4’b0001;
if(key_value==6&key_flag==1)seg_flash_data_r[3:0] <=
{seg_flash_data_r[2:0],seg_flash_data_r[3]};
//左移要调整的位
if(key_value==14&key_flag==1)seg_flash_data_r[3:0] <=
{seg_flash_data_r[0],seg_flash_data_r[3:1]};//右移要调整的位
bcd_seg_display_num_r[15:0] <=
{bcd_min_ten_cnt,bcd_min_one_cnt,bcd_sec_ten_cnt,bcd_sec_one_cnt};
//秒分调整展现界面
if(seg_flash_data_r[0]==1&key_value==13&key_flag==1)begin
if(bcd_sec_one_cnt==9)bcd_sec_one_cnt<=0; else
bcd_sec_one_cnt<=bcd_sec_one_cnt+1;end
if(seg_flash_data_r[1]==1&key_value==12&key_flag==1)begin
if(bcd_sec_ten_cnt==5)bcd_sec_ten_cnt<=0;else
bcd_sec_ten_cnt<=bcd_sec_ten_cnt+1;end
if(seg_flash_data_r[2]==1&key_value==9&key_flag==1)begin
if(bcd_min_one_cnt==9)bcd_min_one_cnt<=0;else
bcd_min_one_cnt<=bcd_min_one_cnt+1;end
if(seg_flash_data_r[3]==1&key_value==8&key_flag==1)begin
if(bcd_min_ten_cnt==5)bcd_min_ten_cnt<=0;else
bcd_min_ten_cnt<=bcd_min_ten_cnt+1;end end

always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
smg_data_r <= 8’b00000000;
else
case (num)
4’d0: smg_data_r <= SEG_NUM0;
4’d1: smg_data_r <= SEG_NUM1;
4’d2: smg_data_r <= SEG_NUM2;
4’d3: smg_data_r <= SEG_NUM3;
4’d4: smg_data_r <= SEG_NUM4;
4’d5: smg_data_r <= SEG_NUM5;
4’d6: smg_data_r <= SEG_NUM6;
4’d7: smg_data_r <= SEG_NUM7;
4’d8: smg_data_r <= SEG_NUM8;
4’d9: smg_data_r <= SEG_NUM9;

reg [24:0]count1;
reg Flag_1S_r;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin count1<=0; Flag_1S_r <= 0; end
else if( count1 == T_half_S)
begin
count1 <= count1 + 1’b1;
Flag_1S_r <=~ Flag_1S_r;
end
else if( count1 == T_1S)
begin
count1<=0;
Flag_1S_r <=~ Flag_1S_r;
end
else
count1 <= count1 + 1’b1;

endmodule

always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
smg_data_r <= 8’b00000000;
else
case (num)
4’d0: smg_data_r <= SEG_NUM0;
4’d1: smg_data_r <= SEG_NUM1;
4’d2: smg_data_r <= SEG_NUM2;
4’d3: smg_data_r <= SEG_NUM3;
4’d4: smg_data_r <= SEG_NUM4;
4’d5: smg_data_r <= SEG_NUM5;
4’d6: smg_data_r <= SEG_NUM6;
4’d7: smg_data_r <= SEG_NUM7;
4’d8: smg_data_r <= SEG_NUM8;
4’d9: smg_data_r <= SEG_NUM9;

2:begin bcd_seg_display_num_r[15:0] <=
{bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
seg_flash_data_r<=4’b0000;end

 

9:
begin start_sig_r <= 1’b0; state<=2; end

parameter T_1S=25000000;
//parameter T_1S=2500;

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
state<=0;
start_sig_r <= 1’b0;
end
else

endmodule

end

reg [2:0]count1;
reg sck_r;

SEG_NUMD=8’h5e,

SEG_NUME=8’h79,

module jishu
(
input clk,
input rst_n,
output [3:0] row_data,
input [3:0] col_data,
output alarm_beep,
output[3:0]seg_flash_data,
output Flag_1S,
output [15:0]bcd_seg_display_num,
input mode_in
);
wire [3:0]key_value;
juzhen key_input
(
.clk(clk),
.rst_n(rst_n),
.col_data(col_data),
.row_data(row_data),
.key_value(key_value),
.key_flag_r0(key_flag1),
.key_flag(key_flag)
);
parameter T_half_S=12500000;
parameter T_1S=25000000;

default: smg_data_r <= 8’b00000000;
endcase
end

parameter
SEG_NUM0=8’h3f,

2: begin
seg_flash_data_r<=4’b0100;
bcd_seg_display_num_r[15:0] <=
{bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if(key_value==5&key_flag==1)begin
if(bcd_hour_one_cnt==9)bcd_hour_one_cnt<=0;else
bcd_hour_one_cnt<=bcd_hour_one_cnt+1;end end

 

SEG_NUM8=8’h7f,

SEG_NUM9=8’h6f,

reg [6:0]state;
reg rck_r;
reg dout_r;
reg done_sig_r;

case (state)
0:
begin duan_wei_data_r[15:0] <= {num2_one_smg_data,8’h27};
state <= state + 1; start_sig_r <= 1’b1; end

来得控制模块

always @(posedge clk or negedge rst_n)
begin
if(!rst_n) begin mode<=0;end
else
begin if(key_in==1) if(mode == 3’b110) mode <= 3’b000;
else mode <= mode + 1’b1;
end
end

assign sck_negedge= (sck_flag2 && ~sck_flag1)?1’b1:1’b0;

// 每一个sck,下跌沿放入数据,上涨沿到,输入输出。 rck
每16个sck拉高三次。

always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin count1<=0; sck_r<=0; end
else if(count1 == 3’d4)
begin count1<=0; sck_r = ~ sck_r; end
else count1 <= count1 +1 ;
end

reg [7:0]smg_data_r;

 

always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
dout_r <= 0;
state <= 0;
done_sig_r <= 1’b0;
end
else
case (state)
0: if(start_sig) state <= state + 1;
1: if(sck_negedge)begin dout_r <= duan_澳门皇冠官网app,wei_data[15]; rck_r
<= 1’b1; state <= state + 1; end
2: if(sck_negedge)begin dout_r <= duan_wei_data[14]; state
<= state + 1; end
3: if(sck_negedge)begin dout_r <= duan_wei_data[13]; state
<= state + 1; end
4: if(sck_negedge)begin dout_r <= duan_wei_data[12]; state
<= state + 1; end
5: if(sck_negedge)begin dout_r <= duan_wei_data[11]; state
<= state + 1; end
6: if(sck_negedge)begin dout_r <= duan_wei_data[10]; state
<= state + 1; end
7: if(sck_negedge)begin dout_r <= duan_wei_data[9]; state <=
state + 1; end
8: if(sck_negedge)begin dout_r <= duan_wei_data[8]; state <=
state + 1; end
9: if(sck_negedge)begin dout_r <= duan_wei_data[7]; state <=
state + 1; end
10: if(sck_negedge)begin dout_r <= duan_wei_data[6]; state
<= state + 1; end
11: if(sck_negedge)begin dout_r <= duan_wei_data[5]; state
<= state + 1; end
12: if(sck_negedge)begin dout_r <= duan_wei_data[4]; state
<= state + 1; end
13: if(sck_negedge)begin dout_r <= duan_wei_data[3]; state
<= state + 1; end
14: if(sck_negedge)begin dout_r <= duan_wei_data[2]; state
<= state + 1; end
15: if(sck_negedge)begin dout_r <= duan_wei_data[1]; state
<= state + 1; end
16: if(sck_negedge)begin dout_r <= duan_wei_data[0]; rck_r
<= 1’b0; state <= state + 1; done_sig_r <= 1’b1; end
17: begin done_sig_r <= 1’b0; state <= 0; end

2:
if(done_sig) begin duan_wei_data_r[15:0] <=
{(seg_flash_data[3]?8’h00:num2_ten_smg_data),Flag_1S?8’h1e:8’h2e};
state <= state + 1; start_sig_r <= 1’b1;
end//{num2_ten_smg_data,4’h2,(4’he&seg_flash_data)}; state <=
state + 1; start_sig_r <= 1’b1; end

SEG_NUM1=8’h06,

数码管解码模块

 

//由0到f的编码为

3:
begin start_sig_r <= 1’b0; state <= state + 1; end

 

wire sck_negedge;

3: begin
seg_flash_data_r<=4’b0010;
bcd_seg_display_num_r[15:0] <=
{bcd_hour_ten_cnt,bcd_hour_one_cnt,bcd_min_ten_cnt,bcd_min_one_cnt};
if(key_value==8&key_flag==1)begin
if(bcd_min_ten_cnt==5)bcd_min_ten_cnt<=0;else
bcd_min_ten_cnt<=bcd_min_ten_cnt+1;end end

(
.clk(clk),
.rst_n(rst_n),
.key_n(mode_in),
.key_pulse (key_in)
);

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